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CS5101
CS5101
Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters
Description
The CS5101 is a bipolar monolithic secondary side post regulator (SSPR) which provides tight regulation of multiple output voltages in AC-DC or DC-DC converters. Leading edge pulse width modulation is used with the CS5101. The CS5101 is designed to operate over an 8V to 45V supply voltage (VCC) range and up to a 75V drive voltage (VC). The CS5101 features include a totem pole output with 1.5A peak output current capability, externally programmable overcurrent protection, an on chip 2% precision 5V reference, internally compensated error amplifier, externally synchronized switching frequency, and a power switch drain voltage monitor. It is available in a 14 lead plastic DIP or a 16 lead wide body SO package.
Features
s 1.5A Peak Output (Grounded Totem Pole) s 8V to 75V Gate Drive Voltage s 8V to 45V Supply Voltage s 300ns Propagation Delay s 1% Error Amplifier Reference Voltage s Lossless Turn On and Turn Off s Sleep Mode: < 100A s Overcurrent Protection with Dedicated Differential Amp s Synchronization to External Clock s External Power Switch Drain Voltage Monitor
Application Diagram
VSY L1
1
TR
CR4
3
Q1
4 5
R10
VOUT
6
R5 R6 CR5
R8
R11
R13 + C6
Package Options
14L PDIP
SYNC
1
R9
R12
R14
VD VC VG PGnd IS COMP ISIS+
Gnd CR1 C5 +
VCC VREF LGnd
R1
R2
CR3
R7
VFB COMP
VSYNC VCC R3 CR2 VREF LGnd VFB + C1 C2 R4 COMP RAMP
VD
RAMP
CS5101 SSPR
VC VG C4
16L SO Wide
SYNC VCC VREF DGnd
1
PGnd IS COMP ISIS+
VD VC VG PGnd PGnd IS COMP ISIS+
2
C3 CR
AGnd VFB COMP RAMP
Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com
Rev. 3/31/97
1
A
Company
CS5101
Absolute Maximum Ratings Power Supply Voltage, VCC .....................................................................................................................................-0.3V to 45V VSYNC and Output Supply Voltages, VC, VG, VSYNC, VD .....................................................................................-0.3V to 75V VIS+, VIS- (VCC 4V, up to 24V)..................................................................................................................................-0.3 to 24V VREF, VFB, VCOMP, VRAMP, VISCOMP ............................................................................................................................-0.3 to 10V Operating Junction Temperature, TJ .......................................................................................................................-40 to 150C Operating Temperature Range ..................................................................................................................................-40 to 85C Storage Temperature Range ....................................................................................................................................-65 to 150C Output Energy (capacitive load per cycle).............................................................................................................................5J ESD Human Body ....................................................................................................................................................................2kV ESD Machine Model...............................................................................................................................................................200V Lead Temperature Soldering Wave Solder (through hole styles only)....................................................................................10 sec. max, 260C peak Reflow (SMD styles only).....................................................................................60 sec. max above 183C, 230C peak Electrical Characteristics: -40C TA 85C; -40C TJ 150C; 10V < VCC < 45V; 8V < VC <75V unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s Error Amplifier Input Voltage Initial Accuracy Input Voltage Input Bias Current Open Loop Gain Unity Gain Bandwidth Output Sink Current Output Source Current VCOMP High VCOMP Low PSRR VFB = VCOMP; VCC = 15V; T = 25C (Note 1) VFB = VCOMP, includes line and temp VFB = 0V; IVFB flows out of pin 1.5V < VCOMP < 3.0V 1.5V < VCOMP < 3.0V; (Note 1) VCOMP = 2.0V; VFB = 2.2V VCOMP = 2.0V; VFB = 1.8V VFB = 1.8V VFB = 2.2V 10V < VCC < 45V; VFB = VCOMP (Note 1) 60 0.7 2 2 3.3 0.85 60 70 1.0 8 6 3.5 1.0 70 3.7 1.15 1.98 1.94 2.00 2.00 2.02 2.06 500 V V nA dB MHz mA mA V V dB
s Voltage Reference Output Voltage Initial Accuracy Output Voltage Line Regulation Load Regulation Current Limit VREF_OK FAULT V VREF_OK V VREF_OK Hysteresis s Current Sense Amplifier IS COMP High V IS COMP Low V Source Current Sink Current Open Loop Gain CMRR PSRR Unity Gain Bandwidth IS+ = 5V; IS = IS COMP IS+ IS+ = 0V; = 5V; IS IS = IS COMP = 0V 4.7 0.5 2.0 10 60 60 60 0.5 5.0 1.0 10 20 80 80 80 0.8 5.3 1.3 V V mA mA dB dB dB MHz VCC = 15V; T = 25C (Note 1) 0A < IREF < 8mA 10V < VCC < 45V; IREF = 0A 0A < IREF < 8mA VREF = 4.8V VSYNC = 5V; VREF = VLOAD VSYNC = 5V; VREF = VLOAD 10 4.10 4.30 40 4.9 4.8 5.0 5.0 10 20 50 4.40 4.50 100 4.60 4.80 250 5.1 5.2 60 60 V V mV mV mA V V mV
IS- = 5V; IS+ = 0V 1.5V VCOMP 4.5V; RL = 4k1/2 (Note 1) 10V < VCC < 45V, (Note 1) 1.5V VCOMP 4.5V; RL = 4k1/2 (Note 1) 2
CS5101
Electrical Characteristics: continued
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s Current Sense Amplifier: continued Input Offset Voltage Input Bias Currents Input Offset Current (IS+, IS-) (Note 1) Input Signal Voltage Range s RAMP/SYNC Generator Ramp Source Current Initial Accuracy Ramp Source Current Ramp Sink Current RAMP Peak Voltage RAMP Valley Voltage RAMP Dynamic Range RAMP Sleep Threshold Voltage SYNC Threshold SYNC Input Bias Current s Output Stage VG, High VG, Low VG Rise Time VG Fall Time VG Resistance to Gnd VD Resistance to Gnd s General ICC, Operating ICC in UVL ICC in Sleep Mode High ICC In Sleep Mode Low IC, Operating High IC, Operating Low UVLO Start Voltage UVLO Stop Voltage UVLO Hysteresis Leading Edge, tDELAY Trailing Edge, tDELAY VSYNC = 2.5V to VG = 8V VSYNC = 2.5V to VG = 2V VSYNC = 5V VCC = 6V VRAMP = 0V; VCC = 45V VRAMP = 0V; VCC = 10V VSYNC = 5V; VFB = VIS = 0V; VC = 75V VSYNC = 5V; VFB = VIS = 0V; VC = 8V 7.4 6.4 0.8 12 300 80 20 4 3 8.0 7.0 1.0 280 750 18 500 200 50 8 6 9.2 8.3 1.2 mA A A A mA mA V V V ns ns VSYNC = 5V; IVG = 200mA, VC VG VSYNC = 0V; IVG = 200mA Switch VSYNC High; CG = 1nF; VCC = 15V; measure 2V to 8V Switch VSYNC Low; CG = 1nF VCC = 15V; measure 8V to 2V Remove supplies; VG = 10V Remove supplies; VD = 10V 500 1.6 0.9 30 40 50 1500 2.5 1.5 75 100 100 V V ns ns k1/2 1/2 VSYNC = 5V, VRAMP = 2.5V ; T = 25C (Note 1) VSYNC = 5V; VRAMP = 2.5V VSYNC = 0V; VRAMP = 2.5V VSYNC = 5V VSYNC = 0V VRAMPDR = VRAMPPK VRAMPVY VRAMP @ VREF < 2.0V VSYNC @ VRAMP > 2.5V VSYNC = 0V; ISYNC flows out of pin 0.18 0.16 1.0 3.3 1.4 1.7 0.3 2.3 0.20 0.20 4.0 3.5 1.5 2.0 0.6 2.5 1 3.7 1.6 2.3 1.0 2.7 20 0.22 0.24 mA mA mA V V V V V A VIS+ = 2.5V; VIS- = VISCOMP VIS+ = VIS- = 0V; IIS flows out of pins -250 -0.3 -8 0 20 0 8 250 250 VCC-4.0 mV nA nA V
Note 1: Guaranteed by design. Not 100% tested in production.
3
CS5101
Package Pin Description
PACKAGE PIN # PIN SYMBOL FUNCTION
14L PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14
16L SO Wide 1 2 3 6 7 8 9 10 11 12, 13 14 15 16 5 4 SYNC VCC VREF LGnd VFB COMP RAMP IS+ ISIS COMP PGnd VG VC VD AGnd DGnd Synchronization input. Logic supply (10V to 45V). 5.0V voltage reference. Logic level ground (Analog and digital ground tied). Error amplifier inverting input. Error amplifier output and compensation. RAMP programmable with the external capacitor. Current sense amplifier non-inverting input. Current sense amplifier inverting input. Current sense amplifier compensation and output. Power ground. External power switch gate drive. Output power stage supply voltage (8V to 75V). External FET DRAIN Voltage Monitor. Analog Ground. Digital Ground. Circuit Description Block Diagram
VCC VCC VREF REF 5V OK + UVL+ + LGnd 8V/7V + SLEEP + 0.7V Q1
VD VC
VG Q2 PGnd IS COMP
VCC 5V 24.6k 5V IS VFB + COMP 2V + 5V 2.4V Q I = 200mA RAMP 5V + RAMP + SYNC 1.65V 5V + SYNC + 2.5V + LATCH Q 1.5V 5V Q4 G1 + REF_OK 0.7V R VCC_OK + S 5V + + + EA 10k 10k BUF + VC + PWM + 5V Q3
ISIS+
+
4.5V/4.4V
VCC
G2
4
CS5101
Circuit Description: continued Theory of Operation The CS5101 is designed to regulate voltages in multiple output power supplies. Functionally, it is similar to a magnetic amplifier, operating as a switch with a delayed turn-on. It can be used with both single ended and dual ended topologies. The VFB voltage is monitored by the error amplifier EA. It is compared to an internal reference voltage and the amplified differential signal is fed through an inverting amplifier into the buffer, BUF. The buffered signal is compared at the PWM comparator with the ramp voltage generated by capacitor CR. When the ramp voltage VR, exceeds the control voltage VC, the output of the PWM comparator goes high, latching its state through the LATCH, the output stage transistor Q1 turns on, and the external power switch, usually an N-FET, turns on. SYNC Function The SYNC circuit is activated at time t1 (Figure 1) when the voltage at the SYNC pin exceeds the threshold level (2.5V) of the SYNC comparator. The external ramp capacitor CR is allowed to charge through the internal current source I (200A). At time t2, the ramp voltage intersects with the control voltage VC and the output of the PWM comparator goes high, turning on the output stage and the external power switch. At the same time, the PWM comparator is latched by the RS latch, LATCH. The logic state of the LATCH can be changed only when both the voltage level of the trailing edge of the power pulse at the SYNC pin is less than the threshold voltage of the SYNC comparator (2.5V) and the RAMP voltage is less than the threshold voltage of the RAMP comparator (1.65V). On the negative going transition of the secondary side pulse VSY, gate G2 output goes high, resetting the latch at time t3. Capacitor CR is discharged through transistor Q4. CROs output goes low disabling the output stage, and the external power switch (an N-FET) is turned off.
RAMP Function The value of the ramp capacitor CR is based on the switching frequency of the regulator and the maximum duty cycle of the secondary pulse VSY. If the RAMP pin is pulled externally to 0.3V or below, the SSPR is disabled. Current drawn by the IC is reduced to less than 100A, and the IC is in SLEEP mode. FAULT Function The voltage at the VCC pin is monitored by the undervoltage lockout comparator with hysteresis. When VCC falls below the UVL threshold, the 5V reference and all the circuitry running off of it is disabled. Under this condition the supply current is reduced to less than 500A. The VCC supply voltage is further monitored by the VCC_ OK comparator. When VCC is reduced below VREF - 0.7V, a fault signal is sent to gate G1. This fault signal, which determines if VCC is absent, works in conjunction with the ramp signal to disable the output, but only after the current cycle has finished and the RS latch is reset. Therefore this fault will not cause the output to turn off during the middle of an on pulse, but rather will utilize lossless turn-off. This feature protects the FET from overvoltage stress. This is accomplished through gate G1 by driving transistor Q4 on. An additional fault signal is derived from the REF_OK comparator. VREF is monitored so to disable the output through gate G1 when the VREF voltage falls below the OK threshold. As in the VCC_OK fault, the REF_OK fault disables the output after the current cycle has been completed. The fault logic will operate normally only when VREF voltage is within the specification limits of REF_OK. DRAIN Function The drain pin, VD monitors the voltage on the drain of the power switch and derives energy from it to keep the output stage in an off state when VC or VCC is below the minimum specified voltage.
VSY 1 0V
VSY
2 VSY + VD
VC VRAMP
VDS 3 0V VSY 4 0V VSY VOUT VL1 5 0V VOUT + VD
VD
VS
VSY + VC 6 0V Ground Level
(Gate doesn't go below Gnd)
VD VG
t1
t2 t3
t4
t1
Figure 1. Waveforms for CS5101. The number to the left of each curve refers to a node on the Application Diagram.
5
CS5101
Circuit Description: continued
S1 8V - 45V C1 1mF SW SPST R1 100k R2 100k VSYNC VCC C2 0.1mF R3 5k VREF LGnd VFB COMP RAMP C4 0.1mF R7 10k VD
V1 100kHz 0V to 5V Square Wave VC VG PGnd IS COMP ISIS+
CS5101 14 L PDIP
C3 1nF
R4 2.2k C5 680pF R5 10k
R6 10k
CS5101 bench test
6
CS5101
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA
D Lead Count 14L PDIP 16L SO Wide Metric Max Min 19.69 18.67 10.50 10.10 English Max Min .775 .735 .413 .398
Thermal Data RQJC typ RQJA typ
16L SOIC 23 105
14L PDIP 48 85
uC/W uC/W
Plastic DIP (N); 300 mil wide
7.11 (.280) 6.10 (.240)
8.26 (.325) 7.62 (.300) 3.68 (.145) 2.92 (.115)
1.77 (.070) 1.14 (.045)
2.54 (.100) BSC
.356 (.014) .203 (.008)
0.39 (.015) MIN. .558 (.022) .356 (.014) Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same.
REF: JEDEC MS-001
D
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299) 7.40 (.291)
10.65 (.419) 10.00 (.394)
0.51 (.020) 0.33 (.013)
1.27 (.050) BSC
2.49 (.098) 2.24 (.088)
2.65 (.104) 2.35 (.093)
1.27 (.050) 0.40 (.016)
REF: JEDEC MS-013
0.32 (.013) 0.23 (.009) D 0.30 (.012) 0.10 (.004)
Ordering Information
Part Number CS5101EN14 CS5101EDW16 CS5101EDWR16
Rev. 3/31/97
Description 14L PDIP 16L SO Wide 16L SO Wide (tape & reel) 7
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
PATENTS PENDING
(c) 1999 Cherry Semiconductor Corporation

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